Timing Violation Prediction in Digital Integrated Circuits Using Temporal Graph Neural Networks
Abstract
With the scale of digital integrated circuit design increasing at about 30% per year, the timing violation problem has become increasingly severe, while the accuracy of traditional detection methods has dropped below 50%. This paper proposes a timing violation prediction method based on a temporal graph neural network (T-GNN). By converting digital integrated circuits into graph structures, applying graph convolutional layers to aggregate structural information, and using LSTM units to capture temporal dependencies, the model achieves significant performance improvements. On the ISCAS85 dataset, the T-GNN model reached 91.2% accuracy, which is nearly 10% higher than the next-best CNN model (81.5%). On the ISCAS89 dataset, the T-GNN achieved 90.7% accuracy, compared to 80.3% for CNN. The recall and F1 values of T-GNN also consistently exceeded 89% on both datasets. These results demonstrate that T-GNN can effectively capture structural and temporal characteristics of circuits, outperform existing rule-based, machine learning, and deep learning methods, thereby providing a reliable and efficient solution for timing violation prediction in digital integrated circuits.References
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