Multipath Priority Scheduling for Store-Forward Optimization in RISC-V Architectures

Abstract

In RISC-V processor design, the Store-Forward processing architecture is used to coordinate data storage and loading operations to avoid collisions. However, as the demand for multi-core and parallel tasks increases, traditional methods face high transmission latency and low bandwidth utilization problems, affecting the overall system performance. Consequently, this paper puts forward a multi - channel priority scheduling mechanism. This mechanism dynamically modulates the priorities of multiple data streams to optimize resource allocation, alleviate congestion, and enhance transmission efficiency. A RISC-V test platform is built based on the Gem5 simulator, and the performance of standard scheduling and multi-channel priority scheduling under data-intensive workloads is compared. The experimental results show that after adopting the new mechanism, the average transmission delay is reduced from 62.3 nanoseconds to 49.8 nanoseconds, which is a reduction of 20%. At the same time, the peak throughput increased from 5GB per second to 6.5 GB, an increase of 30%. In 10000 random data transmission tasks, the scheduling mechanism reduces the processing completion time to 80 milliseconds, which reduces the waiting time by 20% compared to the benchmark of 100 milliseconds. These data indicate that the mechanism effectively mitigates the congestion problem and optimizes resource utilization. The multi-channel priority scheduling mechanism takes multi-source concurrent data streams in the Store Forward path of the RISC-V architecture as the scheduling object, and allocates priority through "static instruction encoding+dynamic weighted calculation" - embedding priority with 3 bits (P [2:0]) in I/S type instructions, and then adjusting priority in real time by the weight calculation unit combined with data waiting time, critical path labeling, and request source attributes. Finally, the optimal forwarding channel is matched through a distributed arbitration unit; In terms of architecture, it is necessary to expand the RISC-V instruction set, modify the pipeline, and integrate priority processing modules. The overall performance will be verified on the RISC-V multi-core platform built on the Gem5 simulator and tested through load tests such as Splash-3 and AlexNet.