Using multi-channel priority scheduling mechanism to improve the transmission efficiency of Store-Forward processing structure under RISC-V architecture

Abstract

In RISC-V processor design, the Store-Forward processing architecture is used to coordinate data storage and loading operations to avoid collisions. However, as the demand for multi-core and parallel tasks increases, traditional methods face high transmission latency and low bandwidth utilization problems, affecting the overall system performance. Therefore, we propose a multi-channel priority scheduling mechanism, which dynamically adjusts the priorities of multiple data streams to optimize resource allocation, reduce congestion, and improve transmission efficiency. A RISC-V test platform is built based on the Gem5 simulator, and the performance of standard scheduling and multi-channel priority scheduling under data-intensive workloads is compared. The experimental results show that after adopting the new mechanism, the average transmission delay is reduced from 60 nanoseconds to 48 nanoseconds, which is a reduction of 20%. At the same time, the peak throughput increased from 5GB per second to 6.5 GB, an increase of 30%. In 1000 random data transmission tasks, the scheduling mechanism reduces the processing completion time to 80 milliseconds, which reduces the waiting time by 20% compared to the benchmark of 100 milliseconds. These data indicate that the mechanism effectively mitigates the congestion problem and optimizes resource utilization. Through multi-channel priority scheduling, the transmission efficiency of the Store-Forward processing structure is significantly improved in the RISC-V environment, providing a feasible solution for high-performance computing applications.