Design of an Asynchronous Processor with Bundled-data Implementation on a Commercial Field Programmable Gate Array

Abstract

In this paper, we propose a modeling method and a design ow to design asynchronous processors with bundled-data implementation on commercial Field Programmable Gate Arrays (FPGAs). The modeling method mainly concerns modeling of an asynchronous control circuit on commercial FPGAs. In addition to the use of a design environment provided by FPGA vendor, the design ow includes constraint generation, timing analysis, and delay adjustment to design asynchronous processor from a prepared model to FPGA programming. In the experiments, we design three asynchronous MIPS processors. Comparing with the synchronous counterpart, one of them reduces global cycle time which results in 13.8% performance improvement and another one reduces energy consumption 9.3% for a multiplication and 8.8% for a matrix multiplication.

Authors

  • Jukiya Furushima University of Aizu
  • Masamitsu Nakajima University of Aizu
  • Hiroshi Saito University of Aizu

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Published

12/23/2016

How to Cite

Furushima, J., Nakajima, M., & Saito, H. (2016). Design of an Asynchronous Processor with Bundled-data Implementation on a Commercial Field Programmable Gate Array. Informatica, 40(4). Retrieved from https://www.informatica.si/index.php/informatica/article/view/1464

Issue

Vol. 40 No. 4 (2016)

Section

Special issue papers

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